On this page, I have attempted to list all of the work I have
been involved with at the University of York in the last year or two. My
curriculum vitae gives a concise
summary that omits most of the details, but covers a longer period of
time. This page is organised by category as follows:
How to manage data accesses predictably
Usually, a CPU accesses data via a cache, which stores copies
of recently accessed data elements. The access time is dependent
on the cache contents, which are in turn dependent on execution
history. This is a source of unpredictability, because it's
hard to know exactly what is in the cache. Under some circumstances,
it is possible to be sure that a particular data element is in
cache, but it's not possible to be sure that an element isn't
in cache, which can be just as problematic for some architectures
(e.g. the trace scratchpad architecture explored in my
thesis).
In my work, this has forced the adoption of
data scratchpads
which have known contents at all times. These can replace caches, but they
make a programmer's job much more difficult. Programmers have to
decide what will be in scratchpad explicitly, and although this
could be assisted by a tool and
justified as a part of designing a system for predictability,
it is a tough requirement that does not accommodate legacy code.
Because a move to "many core" architectures forces an overhaul
of the way that memory is accessed by programs, the current
research climate is an ideal opportunity to find ways to access
memory predictability. The old paradigms for memory access (such as
a single uniform memory space for every program) are not going
to be applicable in a "many core" system, which is exactly the
problem facing a predictable system with a data scratchpad.
The bottlenecks that limit CPU performance
The practical limits of instruction level parallelism and
memory access speculation have now been reached in current CPU cores.
As my publications describe, stricter forms
of the same limits apply to predictable CPUs. A way to write programs
for "many core" architectures would allow performance improvements
beyond the limits of instruction level parallelism, but if it
also allowed predictable programs to be written, it would also
benefit real-time systems.
Adoption of "many core" programming paradigms will be a revolutionary
step in computing history, but predictability will continue to be
important for real-time applications. There are opportunities to use
apply predictability requirements to "many core" research; indeed,
because bandwidth and throughput guarantees are key requirements
for all systems, there is an opportunity to base "many core"
research on real-time principles. However, the challenges are
significant, because computing will need to be partially reinvented at
almost every level of abstraction.
