EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0A fpga_0_BaseBoard_LEDs_3Bit_GPIO_d_out_pin O 0:2 fpga_0_BaseBoard_LEDs_3Bit_GPIO_d_out 1B fpga_0_DDR_SDRAM_32Mx16_DDR_DQ IO 15:0 fpga_0_DDR_SDRAM_32Mx16_DDR_DQ 2B fpga_0_DDR_SDRAM_32Mx16_DDR_DQS IO 1:0 fpga_0_DDR_SDRAM_32Mx16_DDR_DQS 3B fpga_0_DDR_SDRAM_32Mx16_DDR_Addr_pin O 12:0 fpga_0_DDR_SDRAM_32Mx16_DDR_Addr 4B fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr_pin O 1:0 fpga_0_DDR_SDRAM_32Mx16_DDR_BankAddr 5B fpga_0_DDR_SDRAM_32Mx16_DDR_CAS_n_pin O 1 fpga_0_DDR_SDRAM_32Mx16_DDR_CAS_n 6B fpga_0_DDR_SDRAM_32Mx16_DDR_CE_pin O 1 fpga_0_DDR_SDRAM_32Mx16_DDR_CE 7B fpga_0_DDR_SDRAM_32Mx16_DDR_CS_n_pin O 1 fpga_0_DDR_SDRAM_32Mx16_DDR_CS_n 8B fpga_0_DDR_SDRAM_32Mx16_DDR_Clk_n_pin O 1 fpga_0_DDR_SDRAM_32Mx16_DDR_Clk_n 9B fpga_0_DDR_SDRAM_32Mx16_DDR_Clk_pin O 1 fpga_0_DDR_SDRAM_32Mx16_DDR_Clk 10B fpga_0_DDR_SDRAM_32Mx16_DDR_DM_pin O 1:0 fpga_0_DDR_SDRAM_32Mx16_DDR_DM 11B fpga_0_DDR_SDRAM_32Mx16_DDR_RAS_n_pin O 1 fpga_0_DDR_SDRAM_32Mx16_DDR_RAS_n 12B fpga_0_DDR_SDRAM_32Mx16_DDR_WE_n_pin O 1 fpga_0_DDR_SDRAM_32Mx16_DDR_WE_n 13C fpga_0_DIP_Switches_4Bit_GPIO_in_pin I 0:3 fpga_0_DIP_Switches_4Bit_GPIO_in 14D fpga_0_FLASH_2Mx16_Mem_DQ_pin IO 0:15 fpga_0_FLASH_2Mx16_Mem_DQ 15D fpga_0_FLASH_2Mx16_Mem_CEN_pin O 0:0 fpga_0_FLASH_2Mx16_Mem_CEN 16D fpga_0_FLASH_2Mx16_Mem_OEN_pin O 0:0 fpga_0_FLASH_2Mx16_Mem_OEN 17D fpga_0_FLASH_2Mx16_Mem_RPN_pin O 1 fpga_0_FLASH_2Mx16_Mem_RPN 18D fpga_0_FLASH_2Mx16_Mem_WEN_pin O 1 fpga_0_FLASH_2Mx16_Mem_WEN 19E fpga_0_FLASH_2Mx16_Mem_A_pin O 10:30 fpga_0_FLASH_2Mx16_Mem_A 20F JTAG_Host_In_GPIO_in_pin I 0:0 JTAG_Host_In_GPIO_in 21G JTAG_Host_Out_GPIO_d_out_pin O 0:2 JTAG_Host_Out_GPIO_d_out 22H fpga_0_RS232_RX_pin I 1 fpga_0_RS232_RX 23H fpga_0_RS232_TX_pin O 1 fpga_0_RS232_TX				# NAME DIR [LSB:MSB] SIG ATTRIBUTES 24I Relay_Out O 0:1 Relay_Out_TS 25J fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin I 7:0 fpga_0_TriMode_MAC_GMII_GMII_RXD_0 26J fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0 27J fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0 28J fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin I 1 fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0 29J fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin I 1 fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0 30J fpga_0_TriMode_MAC_GMII_MDIO_0_pin IO 1 fpga_0_TriMode_MAC_GMII_MDIO_0 31J fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin O 7:0 fpga_0_TriMode_MAC_GMII_GMII_TXD_0 32J fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0 33J fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0 34J fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin O 1 fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0 35J fpga_0_TriMode_MAC_GMII_MDC_0_pin O 1 fpga_0_TriMode_MAC_GMII_MDC_0 36J fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin O 1 fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n 37K sys_clk_pin I 1 dcm_clk_s  CLK  38L sys_rst_pin I 1 sys_rst_s  RESET  39M uart_0_sin_pin I 1 uart_0_sin 40M uart_0_sout_pin O 1 uart_0_sout 41N uart_1_sin_pin I 1 uart_1_sin 42N uart_1_sout_pin O 1 uart_1_sout 43O uart_2_sin_pin I 1 uart_2_sin 44O uart_2_sout_pin O 1 uart_2_sout 45P uart_3_sin_pin I 1 uart_3_sin 46P uart_3_sout_pin O 1 uart_3_sout